The present invention relates to a method for recovering data to be decoded, and more particularly to a method for recovering nT run length limited (RLL) constrained data to be decoded to user data. The present invention also relates to a device for recovering nT RLL constrained data.
Computer storage systems (such as optical, magnetic, and the like) record digital data onto the surface of a storage medium, which is typically in the form of a rotating magnetic or optical disc, by altering a surface characteristic of the disc. The digital data serves to modulate the operation of a write transducer (write head) which records binary sequences onto the disc in radially concentric or spiral tracks. When reading this recorded data, a read transducer (read head), positioned in close proximity to the rotating disc, detects the alterations on the medium and generates a sequence of corresponding pulses in an analog read signal. These pulses are then detected and decoded by read channel circuitry in order to reproduce the digital sequence.
Detecting and decoding the pulses into a digital sequence can be performed by a simple peak detector in a conventional analog read channel or, as in more recent designs, by a discrete time sequence detector in a sampled amplitude read channel. Discrete time sequence detectors are preferred over simple analog pulse detectors because they compensate for intersymbol interference (ISI) and are less susceptible to channel noise. Consequently, discrete time sequence detectors increase the capacity and reliability of the storage system. There are several well known discrete time sequence detection methods including discrete time pulse detection (DPD), partial response (PR) with Viterbi detection, maximum likelihood sequence detection (MLSD), decision-feedback equalization (DFE), enhanced decision-feedback equalization (EDFE), and fixed-delay tree-search with decision-feedback (FDTS/DF).
When transmitting data or, for example, storing data on a magnetic disk, optical disk, magneto optic disk, or other storage medium, the data is modulated so as to make it suitable for the transmission or storage. An nT run length limited (nT RLL) code is known as one of such modulating codes, wherein T is the bit interval of a channel bit series (storage waveform series) and nT is the minimum inversion interval. In other words, nT RLL encoding constrains to n the minimum number of xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d consecutive bits appearance before inverting to bit xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d.
Please refer to FIG. 1 which is a partial functional block diagram illustrating a conventional optical pickup device. An analog read signal V outputted from a pickup head is processed by a signal processing device that includes a variable gain amplifier 10, an analog-to-digital converter 11, a retiming system 12 and a gain control feedback device 13. The variable gain amplifier 10 adjusts the amplitude of the analog read signal V, and an analog filter (not shown) provides initial equalization toward the desired response as well as attenuating aliasing noise. The analog-to-digital converter 11 asynchronously samples the equalized analog read signal from the analog filter at a time interval T. The asynchronous sample values are applied to the gain control feedback device 13 through and to the retiming system 12 for adjusting the amplitude of the analog read signal V and the frequency and phase of the asynchronous sample values, respectively. The retiming system 12 thus generates synchronous samples Xn. The synchronous samples Xn are then input into a discrete time sequence detector 14, such as a maximum likelihood (ML) Viterbi sequence detector, which detects an estimated binary sequence Bn from the synchronous sample values. A 3T RLL decoder 15, such as a table mapping demodulator, decodes the estimated binary sequence Bn from the sequence detector 14 into estimated user data.
According to the 3T RLL encoding format, essentially single and double repetitive bits are not allowed, i.e. a minimum of three consecutive bits of xe2x80x9c0xe2x80x9ds or xe2x80x9c1xe2x80x9ds is required. Hence, when the binary sequences 111xe2x80x94010xe2x80x94111 and 000xe2x80x94101xe2x80x94000 appear, the binary sequences will be automatically corrected into 111xe2x80x94000xe2x80x94111 and 000xe2x80x94111xe2x80x94000, respectively, thereby recovering the bit data. However, when the following situation happens, it is troublesome to recover data correctly. Please refer to FIG. 2 which is a diagram illustrating the waveform of the analog read signal V, the synchronous sample value sequence Xn and the estimated binary sequence Bn. A preset level Vr is used to determine corresponding high or low levels of the sampling values of the synchronous sample value sequence Xn so as to obtain the estimated binary sequence Bn. For the sample values of the sequence Xn larger than Vr, the corresponding bit values thereof are determined to be xe2x80x9c1xe2x80x9ds, and on the contrary, the bit values are xe2x80x9c0xe2x80x9ds for those sampling values smaller than the preset value Vr. Hence, when the estimated binary sequence Bn is 111xe2x80x941001xe2x80x94111 as shown in FIG. 2, it is sure that there is an error in the sequence Bn because of its origination from the 3T RLL encoding format. The binary sequence Bn is supposed to be either 111xe2x80x940001xe2x80x94111 or 111xe2x80x941000xe2x80x94111. According to the conventional method, however, it cannot determine which sequence is the correct data.
Therefore, the purpose of the present invention is to develop a method and a device for recovering the correct nT RLL constrained data to deal with the above situations encountered in the prior art.
An object of the present invention is to provide a method and a device for recovering nT run length limited (RLL) constrained data to be correctly decoded in an nT RLL decoder.
According to an aspect of the present invention, there is provided a method for recovering a data required to have n consecutive and repetitive xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d bits. The data is obtained by converting a sample value sequence into a binary sequence according to a preset value and the data having nxe2x88x921 consecutive first-level bits and two second-level bits immediately adjacent to two end bits of the nxe2x88x921 consecutive first-level bits, respectively. The method corrects one of the two second-level bits, which has a corresponding sample value closer to the preset value than the other, into another first-level bit to obtain n consecutive first-level bits.
In an embodiment, the first-level bit is bit xe2x80x9c1xe2x80x9d and the second-level bit is bit xe2x80x9c0xe2x80x9d.
In another embodiment, the first-level bit is bit xe2x80x9c0xe2x80x9d and the second-level bit is bit xe2x80x9c1xe2x80x9d.
For example, the preset value can be zero.
For example, n can be equal to 3.
According to another aspect of the present invention, there is provided a device for recovering a data including nxe2x88x921 consecutive first-level bits with two second-level bits immediately adjacent to two end bits of the nxe2x88x921 consecutive first-level bits to a data including n consecutive first-level bits. The device includes a first storing device for storing an analog signal sequence including n sample values, a second storing device for storing a binary sequence that is converted from the sample value sequence according to a preset value so as to include the nxe2x88x921 consecutive first-level bits with the two second-level bits, and a comparative bit detector electrically connected to the first and second storing devices, and correcting one of the two second-level bits in the second storing device, which has a corresponding sampling value in the first storing device closer to the preset value than the other, into another first-level bit to obtain n consecutive first-level bits.
According to a further aspect of the present invention, there is provided a data-recovering device for recovering nT RLL constrained data that is to be used in an nT RLL decoder. The data-recovering device includes a first storing device for storing a sampling value sequence including a plurality of sample values, a second storing device for storing a binary sequence that is converted from the sampling value sequence according to a preset value, and a comparative bit detector electrically connected to the first and second storing devices for detecting whether a specific pattern of nxe2x88x921 consecutive and repetitive bits with a preceding and a following bits different from the nxe2x88x921 consecutive and repetitive bits exists in the second storing device, and correcting one of the preceding and following bits, which has a corresponding analog signal in the first storing device closer to the preset value than the other, to be identical to the nxe2x88x921 consecutive and repetitive bits when the specific pattern is detected.
Preferably, the first and second data storing devices are a first and a second first-in first-out buffers, respectively. In an embodiment, the first and second first-in first-out buffers are a first and a second shift registers, respectively.
Preferably, the first shift register comprises n+1 register units for storing therein n+1 sample values and the comparative bit detector includes a comparator electrically connected to the first one and the last one of the n+1 register units for comparing two end ones of the n+1 sample values with each other, and outputting a correcting signal with the information that which register unit stores therein the sample value closer to the preset value than the other, and a detecting and correcting device electrically connected to the comparator and the second shift register for detecting the specific pattern, and correcting the preceding or the following bit in the second shift register in response to the correcting signal.
Preferably, n is equal to 3.